Intel brings 18A node to budget mobile chips with Wildcat Lake

Intel has unveiled the architecture of Wildcat Lake, a budget-oriented mobile SoC that brings the company's most advanced manufacturing process to the entry-level market. Detailed at Hot Chips 2026, the chip represents a departure from traditional budget hardware by utilizing the cutting-edge 18A node for its compute capabilities.

To keep costs low while using premium silicon, Intel opted for a Multi-Chip Package (MCP) design. Rather than employing expensive 2.5D or 3D packaging like Foveros, Wildcat Lake uses the Universal Chiplet Interconnect Express (UCIe) open standard to link its components. The SoC is split between a compute die built on the 18A node and an I/O die utilizing ISMC's N6 node. To further reduce expenses, Intel integrated a USB PD controller and Wi-Fi 7 directly into the design and reduced the PCB complexity from eight layers to six.

A break from the 'N-1' tradition

Historically, budget mobile processors have followed an "N-1" design philosophy, where manufacturers use older, cheaper intellectual property to maintain profit margins. Wildcat Lake breaks this trend by applying Intel's latest and most expensive compute IP to the budget domain, according to Lance Hacking, Lead Engineer on Wildcat Lake.

However, integrating the UCIe standard introduced its own overhead in terms of power and die area. To offset these increases, Intel aggressively trimmed both dies. The compute die saw its Xe cores reduced from four to two, NPU tiles cut from three to one, and the memory bus narrowed to 64-bit. Additionally, the I/O die was streamlined by removing the camera PHY.

Optimizing for value

Efficiency was also found in the communication speed between chiplets. While UCIe is capable of 64 GT/s, Intel capped the transfer rate of Wildcat Lake at 8 GT/s. This decision was made to minimize bit-rate errors, which in turn eliminated the need for complex and costly bit-correction systems.

This strategic shift demonstrates that high-end nodes like 18A can be viable for entry-level hardware if paired with open standards and aggressive optimization. By proving that chiplet-based designs can scale down to budget tiers without requiring the most expensive packaging solutions, Intel is potentially redefining the economics of entry-level PC hardware to better compete with the Snapdragon C and MacBook Neo.

What to watch

As Intel moves toward production, the industry will be watching to see if the aggressive trimming of NPU and GPU cores impacts real-world performance enough to offset the gains of the 18A node. While the architectural blueprint is now public, final benchmarks will determine if this value-focused approach can successfully disrupt the budget mobile segment.