NEO Semiconductor Validates 3D X-DRAM Proof-of-Concept to Break Memory Scaling Limits

NEO Semiconductor has announced successful proof-of-concept (POC) results for its 3D X-DRAM technology, a new architecture designed to overcome the physical scaling limits of traditional memory. The breakthrough arrives as the AI boom drives an unprecedented demand for high-density memory solutions.

Developed in collaboration with National Yang Ming Chiao Tung University (NYCU) and fabricated at the National Institutes of Applied Research-Taiwan Semiconductor Research Institute (NIAR-TSRI), the POC demonstrates a 3D NAND-like approach to DRAM. According to company data, the technology achieved read/write latency of less than 10 nanoseconds and endurance exceeding 10¹⁴ cycles. Notably, data retention at 85°C was measured at over one second, which is more than 15 times the 64ms JEDEC standard. To accelerate the path toward commercialization, NEO Semiconductor has also secured a strategic investment led by Stan Shih, the founder of Acer.

The Shift to 3D Architectures

The memory industry is currently facing a critical bottleneck. The surge in Large Language Models (LLMs) has created a massive appetite for High-Bandwidth Memory (HBM), leading to widespread supply shortages. Conventional 2D DRAM scaling is reaching its physical limits, making it increasingly difficult to increase capacity without compromising stability or energy efficiency. This has pushed the industry toward 3D architectures, which stack memory cells vertically to increase density and reduce the physical footprint of the chip.

Implications for AI Infrastructure

If successfully commercialized, 3D X-DRAM could fundamentally alter the economics of AI hardware. Because the technology can be manufactured using existing 3D NAND infrastructure, equipment, and materials, it potentially offers a more cost-effective scaling path than developing entirely new fabrication processes. "These results validate a new scaling path for DRAM," said Andy Hsu, Founder and CEO of NEO Semiconductor. "We believe this technology can enable significantly higher density, lower cost, and improved energy efficiency for the AI era."

By bypassing the bottlenecks of traditional 2D scaling, 3D X-DRAM could lower the energy consumption of data-centric AI systems while providing the massive capacity required for next-generation infrastructure. Jeongdong Choe, Senior Technical Fellow and SVP at TechInsights, noted that the silicon POC represents a significant milestone by demonstrating real-world viability beyond theoretical concepts.

The Path Forward

While the POC validates the technical feasibility of the architecture, the focus now shifts to scaling the technology for mass production. Industry observers will be watching to see how NEO Semiconductor integrates this architecture into existing supply chains and whether it can maintain these performance metrics at higher capacities. While the company aims to overcome the capacity issues plaguing current DRAM, the timeline for full-scale commercial deployment remains to be seen.