NYCU and TSMC Boost 2D Transistor Performance via Interface Engineering

Researchers from National Yang Ming Chiao Tung University (NYCU) and TSMC Corporate Research have developed a monolayer molybdenum disulfide (MoS2) transistor that overcomes long-standing performance limits of 2D semiconductors. By engineering the atomic interface between the channel and the dielectric, the team has created a device that maintains high efficiency at an atomic scale.

The team achieved this by introducing an epitaxial aluminum layer that was subsequently oxidized to create an aluminum oxide buffer layer approximately 0.42 nm thick. This buffer was placed between the MoS2 channel and a hafnium oxide high-κ dielectric. According to research published in Nature Electronics, this architecture reduced electron scattering and improved gate control. Devices featuring 100 nm channels reached a maximum transconductance of 0.45 mS μm-1, operating with an equivalent oxide thickness (EOT) of approximately one nanometer.

The 2D Semiconductor Challenge

As traditional silicon transistors approach atomic scales, they become increasingly difficult to control. Two-dimensional semiconductors like MoS2 are promising alternatives because they can remain extremely thin—approximately 0.7 nm—without losing their crystal structure. However, a persistent technical hurdle has been the deposition of insulating gate dielectrics. Because MoS2 surfaces lack "dangling bonds," depositing dielectrics directly onto the material often creates defects that scatter electrons. This has historically forced a trade-off between the thickness of the dielectric and the mobility of the carriers.

Implications for Chip Architecture

This breakthrough shifts the industry focus from the search for entirely new semiconductor materials toward the engineering of atomic interfaces between existing ones. By solving the interface problem, the researchers have demonstrated a viable path toward scalable, high-performance 2D transistors. This approach reduces a fundamental trade-off that has limited 2D transistors for years, treating the interface as an active part of the device rather than just a boundary.

Path to Manufacturing

Crucially, the transistors were fabricated using chemical vapor deposition (CVD)-grown monolayer MoS2. This method is significantly more relevant to wafer-scale manufacturing than the use of exfoliated flakes, which are common in laboratory settings but impractical for mass production. If these results can be scaled, these 2D transistors could eventually replace or augment silicon in low-power logic and next-generation chip architectures. The industry will now watch to see if this epitaxial interface approach can be applied to other 2D materials to further push the limits of Moore's Law.