FIBER GPU Architecture Decouples Registers to Boost LLM Performance
Researchers propose a new execution model that breaks the link between threads and private registers to accelerate mixed AI workloads.
Researchers from Shanghai Jiao Tong University, the National University of Singapore, and Huawei have introduced FIBER, a GPU architecture designed to decouple execution instances from private register ownership. This shift aims to eliminate critical bottlenecks in modern AI workloads that frequently interleave heavy matrix multiplications with diverse non-GEMM operations.
By extending the traditional single instruction, multiple thread (SIMT) model, FIBER allows execution instances—termed "fibers"—to carry only minimal control state while accessing a shared view of the Streaming Multiprocessor's (SM) registers. This decoupling enables fine-grained dataflow scheduling and dynamic parallelism scaling, allowing the hardware to adapt more fluidly to the varying demands of tensor computation.
The Bottleneck in Tensor Computation
Modern GPUs rely heavily on Tensor Cores to accelerate AI. The method of supplying operands has evolved from register-based systems in the NVIDIA Ampere architecture to memory-based systems in the Hopper and Blackwell generations. Despite these advances, fixed parallelism and coarse-grained scheduling often create inefficiencies. When AI models mix General Matrix Multiply (GEMM) operations with other tasks, the rigid association between a thread and its registers can limit throughput and increase latency.
Performance Gains Across Architectures
According to research published on arXiv, the FIBER model delivers significant performance improvements across multiple NVIDIA GPU generations. In typical mixed-precision LLM serving scenarios, the architecture achieves a 2.25x end-to-end speedup on the Ampere architecture.
The gains extend to newer hardware as well. The researchers report performance increases of 1.8x on the Hopper architecture and 2.09x on the Blackwell architecture. At the kernel level, the performance gains are even more pronounced, reaching up to 2.49x.
Implications for AI Hardware
As Large Language Models (LLMs) grow in complexity, the diversity of their computational requirements increases. The ability to dynamically scale parallelism and manage register dataflow more efficiently is critical for reducing latency and increasing overall throughput. FIBER provides a technical blueprint for evolving GPU Instruction Set Architectures (ISAs) and microarchitectures to better support the heterogeneous nature of modern tensor computation.
Future Outlook
While current results demonstrate substantial theoretical and simulated gains, the industry will be watching to see if these decoupled execution models are integrated into future commercial silicon. The transition from fixed register ownership to a shared fiber-based view represents a fundamental shift in how GPUs handle the massive data movement required by next-generation AI.