Jane Street Challenges Engineers to Reverse Engineer ASIC from Layout File

Jane Street has released a technical puzzle that tasks participants with reverse engineering an Application-Specific Integrated Circuit (ASIC) using only its GDS layout file. The challenge serves as a high-stakes test of hardware analysis skills, requiring solvers to derive functional logic from physical geometry.

To complete the puzzle, participants were provided with a GDS file—the geometric description of the chip—alongside sample inputs and outputs. However, the challenge offered no labels or source code to guide the process. According to the Jane Street Blog, "The GDS is, in a very real sense, the chip. Everything the circuit does is in there. The tricky part: nothing is labeled!"

Participants had to recover a netlist from the layout, determine the circuit's overall purpose, and simulate the resulting logic to extract a specific final string answer. To assist users in familiarizing themselves with the necessary tools, Jane Street provided a "warm-up" example featuring a simple binary adder, including both its GDS and Verilog source. The puzzle repository was hosted on GitHub at janestreet/asic-puzzle-2026.

The Complexity of Hardware Recovery

This challenge reflects the inherent difficulty of hardware reverse engineering, where the "source code" is effectively a map of physical polygons. Unlike software reverse engineering, where a compiler may leave behind symbols or structured assembly, an ASIC layout is a physical representation of transistors and wires. Recovering a netlist from such a file requires a deep understanding of how physical layers translate into logic gates and how those gates are interconnected to form a functional system.

Recruitment and Branding

Jane Street frequently publishes high-difficulty technical puzzles to attract specialized talent and showcase the problem-solving rigor required by its hardware team. The firm designs FPGAs and ASICs specifically for high-frequency trading, where nanoseconds of latency can determine profitability. By emphasizing the use of tools like Hardcaml and a focus on low-level optimization, the firm uses these challenges as both a recruitment tool and a branding exercise to signal its technical sophistication to the engineering community.

What's Next

While the puzzle provides a glimpse into the firm's hardware philosophy, the full extent of the circuit's complexity remains a point of discussion among the participants. Observers will be watching to see if Jane Street continues this trend of hardware-centric challenges to further build its pipeline of engineers capable of operating at the intersection of physical layout and high-level logic.