Jane Street Challenges Engineers to Reverse Engineer Custom ASIC
The quantitative trading firm has released a GDS layout file, tasking participants with recovering a circuit's logic from its physical blueprint.
Jane Street has launched a technical puzzle that challenges participants to reverse engineer a custom-designed application-specific integrated circuit (ASIC). The firm is asking engineers to recover a netlist from a physical layout to uncover the circuit's purpose and a hidden string value.
To facilitate the challenge, Jane Street provided a GDS layout file, which contains the geometric descriptions of all metal, routing, and active transistor layers used during fabrication. Participants are also given sample inputs and outputs to help deduce the chip's behavior. To assist those unfamiliar with the process, the firm included a warm-up example featuring a simple binary adder, complete with its Verilog source, gate-level netlist, and GDS file. All puzzle materials are hosted on GitHub in the janestreet/asic-puzzle-2026 repository, with a submission deadline of September 4, 2026.
The Hardware Engineering Hurdle
Jane Street's hardware team specializes in developing FPGAs and ASICs tailored for high-frequency trading systems. This challenge is part of a broader series of technical puzzles—including a previous neural network challenge—designed to attract engineering talent. The firm's hardware roles typically require the ability to analyze gates, timing reports, and waveforms, making this puzzle a reflection of the actual problem-solving required in their production environment.
Implications for Hardware Security
This exercise underscores the immense complexity of hardware security and the difficulty of reverse engineering. By providing the GDS file—the same "blueprint" sent to foundries such as Intel or TSMC—Jane Street demonstrates a critical security reality: possessing the physical layout of a chip does not automatically grant access to its logic. Recovering a functional netlist from a raw layout without labels remains a significant technical barrier, highlighting the gap between physical fabrication data and logical understanding.
What to Watch
As the September deadline approaches, the industry will be watching to see how many participants successfully bridge the gap from geometry to logic. While the warm-up adder provides a baseline, the primary puzzle's complexity remains the central test. It remains to be seen how many engineers can successfully extract the specific string value required for a winning submission.