Samsung and XCENA Debut MX1 CXL Device to Solve AI Memory Bottlenecks
The Memory Xcelerator combines near-memory compute and SSD storage to expand capacity for massive ML models.
Samsung and XCENA have introduced the MX1, a Compute Express Link (CXL)-based memory expansion device designed to meet the escalating capacity demands of modern machine learning models. Unveiled at Hot Chips 2026, the device aims to break the traditional limits of server memory architectures.
Known as the Memory Xcelerator, the MX1 goes beyond simple capacity increases. According to technical details presented at the event, the device integrates CXL memory expansion with SSD-backed storage—presented as byte-addressable memory—and near-memory compute capabilities powered by RISC-V cores. This hybrid approach allows the device to host storage and execute processing tasks directly on the expansion module rather than relying solely on the host CPU.
The AI Memory Crunch
The development of the MX1 comes as the rise of Large Language Models (LLMs) and complex AI workloads has created an insatiable appetite for memory. Traditional server architectures are limited by the number of direct memory channels available to the CPU, creating a ceiling on how much data can be kept in high-speed memory. CXL provides a standardized interconnect that allows servers to expand these memory pools, enabling the attachment of external memory resources that the system can treat as local.
Reducing Data Bottlenecks
By implementing near-memory compute, the MX1 addresses one of the primary inefficiencies in AI infrastructure: the constant movement of massive datasets between storage, memory, and the processor. Moving compute operations closer to where the data resides reduces latency and minimizes the energy and time wasted on data transport. The integration of SSDs on the same CXL device further streamlines this pipeline, allowing for a more efficient transition between persistent storage and active memory for memory-intensive workloads.
The Path Forward
As AI models continue to grow in parameter count, the industry is shifting toward disaggregated memory architectures where resources can be scaled independently of the CPU. The MX1 represents a move toward more intelligent memory expansion that does not just store data but actively processes it. Future adoption will likely depend on how seamlessly these RISC-V cores integrate with existing AI software stacks and the overall performance gains realized in production LLM environments.