ASML and TSMC Partner on 12-Inch High-NA EUV Photomasks

ASML and TSMC have launched a joint industry initiative to develop 12-inch photomasks for High Numerical Aperture (High-NA) extreme-ultraviolet (EUV) lithography. The project seeks to overhaul current mask standards to enable the production of larger, more complex semiconductors without the technical limitations of existing exposure fields.

The initiative targets a 12-inch mask pilot line by 2031, with full production-system readiness for advanced-node manufacturing expected by 2033. Samsung has also committed to joining the effort. Currently, High-NA EUV tools utilize 6-inch masks, which create a smaller exposure field. For large-scale chips, this requires "stitching," a process where multiple exposures are combined to form a single circuit. According to ASML Chief Technology Officer Marco Pieters, transitioning to the larger mask format could increase system productivity by approximately 40 percent.

The High-NA Roadmap

High-NA EUV represents the next evolution of lithography, designed to print finer features on silicon to sustain Moore's Law. While Intel has already begun installing these systems, other industry leaders are following a staggered timeline. TSMC plans to begin high-volume manufacturing for advanced logic nodes starting in 2030, while Samsung and SK Hynix are targeting 2028 for the mass production of DRAM using the technology.

The shift to 12-inch masks is categorized as a second-stage productivity roadmap. This transition is not a prerequisite for the initial deployment of High-NA technology, but rather an optimization intended to scale efficiency once the initial systems are operational.

Implications for AI Hardware

The move toward larger masks is primarily driven by the demands of the AI revolution. Massive AI accelerators and high-bandwidth memory (HBM) designs require significant chip area to house the billions of transistors necessary for complex neural networks. By removing the stitching constraint, manufacturers can produce these larger dies more efficiently.

Beyond physical chip size, the initiative aims to reduce manufacturing costs. Eliminating the need for multiple exposures per chip reduces the time a wafer spends in the scanner, increasing overall fab throughput. This efficiency is critical as the industry moves toward nodes where lithography costs represent a growing share of total production expenses.

Future Outlook

As the industry moves toward the 2031 pilot target, the focus will shift to the materials science and precision engineering required to maintain mask flatness and accuracy at a 12-inch scale. While the commitment from ASML, TSMC, and Samsung signals a broad industry consensus, success depends on the seamless integration of these larger masks into the High-NA scanner architecture. Observers will be watching for further technical milestones as the 2030 high-volume manufacturing window for logic nodes approaches.