Skytech Shifts to Panel-Level Packaging to Scale AI Chip Production
The Taiwanese equipment maker is deploying next-generation PVD tools to replace round wafers with higher-yield square substrates.
Taiwanese semiconductor equipment manufacturer Skytech Inc is repositioning itself as a primary provider of advanced packaging infrastructure to meet the scaling demands of the AI boom. The company is now delivering next-generation physical vapor deposition (PVD) equipment designed for fan-out panel-level packaging (PLP), a shift that marks its transition from a spare-parts supplier to a full-scale equipment provider.
In January 2026, Skytech delivered its first PLP commercialization equipment—also referred to as chip-on-panel-on-substrate (CoPoS)—to a strategic customer located in Kaohsiung. This deployment is a cornerstone of the company's growth strategy, which is expected to drive record-high revenue in 2026, surpassing the NT$2.59 billion peak seen in 2024. Beyond packaging, the company is also developing EUV pellicle inspection tools with the goal of becoming the world's second supplier of the technology after EUV Tech Inc.
The Shift to Square Substrates
Most current high-performance AI chips rely on chip-on-wafer-on-substrate (CoWoS) packaging, which utilizes traditional 12-inch round wafers. However, as AI chips increase in physical size, the industry is hitting capacity and yield constraints inherent to circular wafers. PLP technology addresses this by moving to 310mm x 310mm square substrates.
According to Skytech CEO George Yi, this geometric shift significantly boosts output. Yi noted that a single panel-level substrate can produce nine AI chips, representing a 2.25x increase over the four chips typically cut from a standard 12-inch round wafer. By maximizing the usable surface area, PLP allows manufacturers to scale the production of massive AI accelerators more efficiently than previous methods allowed.
Industry Implications
This transition is critical for the broader AI hardware market, where the bottleneck has shifted from chip design to the physical ability to package these components at scale. By delivering tools that succeed CoWoS technology, Skytech is embedding itself into the core infrastructure required for the next generation of high-performance computing.
Skytech is leveraging Taiwan's dense semiconductor ecosystem to outmaneuver larger global competitors. "One of our winning strategies is ‘speed’ against bigger global rivals," Yi stated, highlighting the company's intent to rapidly roll out tools that can be integrated into existing fabrication workflows.
Future Outlook
As the industry moves toward CoPoS, the primary metric for success will be the stability and yield of these larger square panels. While Skytech has successfully delivered its first commercial unit, the broader adoption of PLP across the AI supply chain remains the key variable for the company's long-term revenue trajectory. Market observers will be watching for further deployments and the official entry of Skytech's EUV inspection tools into the global market.