Synopsys and A*STAR Partner to Accelerate AI Chip Packaging via Digital Simulation
The collaboration leverages Ansys tools to reduce physical prototyping costs for chiplet and System-in-Package architectures.
Synopsys and Singapore's Agency for Science, Technology and Research (A*STAR) have signed a Memorandum of Understanding to advance semiconductor packaging and simulation technologies. The partnership aims to accelerate the development of high-performance computing (HPC) and AI hardware by shifting design validation from physical trials to digital modeling.
The collaboration is executed through the ASTAR IME–Ansys Joint Innovation Consortium for Semiconductor Excellence (JICSE). By utilizing Ansys simulation tools—which are now part of Synopsys—the partnership focuses on chiplet-based architectures and System-in-Package (SiP) technologies. To facilitate this, Synopsys is providing trial licenses of Ansys simulation software to ASTAR IME and up to ten member companies within the consortium.
The Shift to System-Driven Design
As AI and HPC drive the need for increasingly complex semiconductor systems, traditional physical prototyping has become prohibitively costly and time-consuming. The industry is shifting toward "More than Moore" strategies, where system-level integration and advanced packaging are as critical to performance as the scaling of individual transistors.
According to Terence Gan, Executive Director at A*STAR IME, advanced packaging is becoming a critical differentiator in global semiconductor innovation as AI-driven systems grow in complexity. This partnership addresses that complexity by employing a simulation-led, system-driven design approach. The initial phase of JICSE specifically targets mechanical design and analysis to identify reliability issues before a physical chip is produced. Key technical focus areas include mitigating wafer warpage, managing thermo-mechanical stress, ensuring solder joint reliability, and preventing moisture-induced failures.
Industry Implications
By replacing iterative physical trial-and-error with high-fidelity digital modeling, the partnership reduces time-to-market and development costs for next-generation AI hardware. This approach allows engineers to pinpoint performance bottlenecks and structural weaknesses in a virtual environment, streamlining the path to mass production.
Beyond the technical gains, the move strengthens Singapore's strategic position as a global semiconductor hub. By bridging the gap between academic research and industrial application, the consortium creates a pipeline for the rapid commercialization of packaging innovations.
Future Outlook
As the collaboration progresses, the focus will remain on the effective integration of complex systems. Sukhwan Moon, Vice President APAC, Sales at Synopsys, noted that the future of semiconductor innovation will be defined by how effectively these complex systems are designed and integrated. Observers will be watching how the ten consortium member companies utilize the trial licenses to implement these simulation-led workflows in commercial AI chip production.