TSMC and Samsung Commit to ASML High-NA EUV for AI Chip Scaling
The semiconductor giants are preparing for next-generation lithography, though TSMC is delaying high-volume production until 2030.
TSMC and Samsung have committed to adopting ASML's High-NA (High Numerical Aperture) EUV lithography systems to increase chip density for AI workloads. This transition ensures foundries can continue scaling transistor density as AI demands push the limits of current silicon manufacturing.
Each High-NA EUV machine costs approximately $400 million, representing a massive capital investment. While Intel was the first customer to receive and deploy these systems—targeting their use in the 14A node—TSMC is taking a more measured approach. Reports indicate that TSMC intends to bring High-NA technology into high-volume production for its advanced nodes starting in 2030.
The Path to Mass Production
To facilitate the transition to high-volume manufacturing, ASML and TSMC are collaborating to advance EUV mask sizes. The industry is working to push these masks from 6 inches to 12 inches, a critical technical shift required to support the throughput and precision of High-NA mass production.
This technical evolution comes as foundries balance the extreme cost of new hardware against the capabilities of existing tools. Extreme Ultraviolet (EUV) lithography is currently the gold standard for printing the smallest features on silicon, but High-NA is the next generation, offering the higher resolution and density necessary for the next decade of chip design.
Strategic Divergence
Despite the eventual commitment to the technology, TSMC is extending the utility of its current fleet. The company has explicitly stated that it does not require High-NA EUV for its N2, N2P, or A16 process technologies. By utilizing multi-patterning with standard EUV, TSMC is opting for a cost-benefit strategy that avoids the immediate $400 million-per-unit expenditure while Intel aggressively pursues a lead in the 14A node.
This divergence highlights the tension between rapid innovation and economic viability. For TSMC, the goal is to maintain leadership in the 1.4nm-class process technology without prematurely adopting hardware that may not yet offer a sufficient return on investment for its current roadmap.
Industry Implications
The adoption of High-NA EUV is critical for the continued scaling of Moore's Law. As AI chips require increasingly complex transistor designs to improve power efficiency and performance, the ability to mass-produce these designs economically will determine the market leadership of the world's top foundries.
What to Watch
Industry observers will be monitoring whether TSMC's cautious timeline holds or if competitive pressure from Intel's 14A deployment forces an acceleration of the 2030 target. Additionally, the successful transition of EUV masks to 12 inches remains a pivotal technical milestone that must be achieved before High-NA can move from experimental deployment to true high-volume manufacturing.