Google Taps AMD for Hybrid TPU v10 to Accelerate Agentic AI

Google is reportedly partnering with AMD to design its next-generation Tensor Processing Unit (TPU), marking a strategic shift in the company's custom silicon roadmap. The collaboration aims to produce a hybrid AI ASIC that integrates on-package CPU cores to optimize specific high-compute workloads.

According to reports, the upcoming hardware—identified as TPU v10—will move beyond a pure accelerator design. By embedding CPU cores directly on the package, Google intends to optimize the chip specifically for reinforcement learning (RL) and agentic AI workloads. This architectural change allows the hardware to handle the complex decision-making logic and environment simulations inherent to RL more efficiently than traditional decoupled systems.

The Push for Silicon Independence

Google has a long history of developing its own TPUs to reduce systemic reliance on NVIDIA GPUs and to tailor hardware to its specific software stack. While previous TPU iterations focused primarily on the massive matrix multiplications required for deep learning, the shift toward a hybrid model reflects the evolving nature of AI. Modern agentic AI requires a tighter loop between the AI accelerator and general-purpose processing to minimize the time it takes for a model to perceive an environment and execute an action.

Solving the Latency Bottleneck

This hybrid approach is critical because reinforcement learning often suffers from significant data movement bottlenecks. In standard configurations, the AI accelerator must constantly communicate with a separate CPU to process environment states, creating latency that slows down training and inference. By integrating CPU cores on-package, Google can significantly reduce this latency and streamline the data path, allowing for faster iterations in RL training.

A Strategic Shift in Design

Partnering with AMD suggests that Google is looking to leverage AMD's expertise in chiplet architecture and high-performance integration. AMD has pioneered the use of mixed-die packages in its EPYC and Ryzen lines, a capability essential for creating a stable, high-bandwidth hybrid ASIC. This move signals a broader industry trend where hyperscalers are no longer just designing accelerators, but are rethinking the entire compute package to support the next wave of autonomous AI agents.

What to Watch

While the partnership is reported, the exact specifications and release timeline for the TPU v10 remain unconfirmed. Industry observers will be watching to see if this hybrid architecture becomes the new standard for AI hardware, potentially forcing other chipmakers to integrate more general-purpose compute into their specialized AI silicon to remain competitive in the race for agentic AI.