TSMC and Samsung Commit to ASML High-NA EUV Tools for AI Chip Race
The world's largest foundries are aligning roadmaps for ASML's next-generation lithography to sustain semiconductor scaling.
TSMC and Samsung have committed to adopting ASML's next-generation High Numerical Aperture (High-NA) Extreme Ultraviolet (EUV) lithography tools. The move comes as surging demand for advanced AI chips necessitates smaller, more complex semiconductors that push the limits of current manufacturing capabilities.
These High-NA EUV machines represent a significant leap in precision, increasing the numerical aperture from 0.33 to 0.55. This allows for 1.7x finer patterning resolution compared to standard EUV, improving resolution from approximately 13nm down to 8nm. However, this precision comes with a massive price tag; a single High-NA EUV machine is estimated to cost between $380 million and $400 million.
The Race for 2nm and Beyond
The semiconductor industry is locked in a high-stakes race to reach the 2nm process node and beyond. ASML holds a global monopoly on EUV lithography, making its tool delivery the primary bottleneck for the entire AI chip ecosystem. Intel took an early lead in this cycle, becoming the first company to receive and deploy High-NA EUV shipments to gain a competitive edge in its foundry ambitions. This early move by Intel has forced TSMC and Samsung to accelerate their own adoption plans despite the extreme capital expenditure required.
Industry Implications
The transition to High-NA EUV is critical for the continued scaling of Moore's Law. Without these tools, the industry cannot reliably produce the transistor densities required for the next generation of high-performance computing and AI accelerators. The commitment from TSMC and Samsung ensures that the most advanced AI hardware will have a viable manufacturing path. However, this reliance reinforces ASML's position as the single most influential point of failure in the global technology supply chain, as the entire roadmap for advanced silicon depends on a single supplier's output.
Roadmaps and Timelines
While the commitment to the technology is clear, the timing of high-volume manufacturing varies. Intel remains the first mover, while TSMC and Samsung are managing their integration timelines. Reports indicate that TSMC is delaying adoption until 2029-2030, prioritizing cost-efficiency by utilizing multi-patterning on existing 0.33 NA tools. Samsung's timeline is also shifting, with some reports suggesting a 2030 target for 1nm nodes. The industry will be watching closely to see if these delayed timelines impact the delivery of next-generation AI hardware or if existing tools can bridge the gap.