Lam Research Scales AI Chip Production with Panel-Level Packaging

Lam Research is expanding its semiconductor capabilities into Panel-Level Packaging (PLP), a transition that replaces traditional round wafers with large square or rectangular carrier substrates. This strategic shift is designed to support the increasing size and complexity of AI chips by maximizing throughput and reducing the cost of each individual unit.

To enable this transition, Lam has introduced specialized hardware tailored for larger formats. The Kallisto tool allows for fine line plating of less than 10µm on panels measuring up to 1.1 meters by 1.3 meters. Complementing this is the PHOENIX tool, which is engineered for 515 mm x 510 mm panels and can process up to 120 panels per hour. PLP allows for more chips per area compared to traditional wafer-level packaging, which directly lowers per-unit manufacturing costs.

The Evolution of Scaling

As artificial intelligence demands more powerful computational capabilities and faster processing of massive datasets, the industry is moving beyond the limits of traditional semiconductor scaling, often referred to as Moore's Law. Advanced packaging has become a critical supplement to this process. Current techniques, including 2.5D and 3D integration as well as Chip on Wafer on Substrate (CoWoS)—the technology utilized in NVIDIA's H100—allow logic and High Bandwidth Memory (HBM) to be integrated more tightly. PLP represents the next evolutionary step, allowing manufacturers to scale these advanced processes beyond the physical constraints of the standard 300mm wafer.

Economic Impact on AI Hardware

This transition is critical for the economic scaling of AI hardware. By moving from round wafers to large rectangular panels, manufacturers can significantly increase the number of chips produced in a single batch. This efficiency is essential for the creation of larger, more complex chiplet architectures required for next-generation GPUs and AI accelerators. The financial stakes are substantial; the advanced packaging market is projected to reach $119.4 billion by 2032.

The Path Forward

Industry observers are now watching how quickly the ecosystem can transition to these larger formats. While the technical capabilities of tools like Kallisto and PHOENIX provide a roadmap for scaling, the broader adoption of PLP will depend on how effectively manufacturers can integrate these rectangular substrates into existing supply chains. The focus remains on whether this shift can keep pace with the accelerating demand for AI-driven compute power.