TSMC develops silicon bridge packaging to rival Intel's EMIB
The world's largest foundry is expanding its advanced packaging roadmap to offer a more cost-effective alternative to its dominant CoWoS technology.
Taiwan Semiconductor Manufacturing Company (TSMC) is developing a localized silicon bridge packaging technology similar to Intel's Embedded Multi-die Interconnect Bridge (EMIB). The move signals a strategic shift to provide AI chip customers with more flexibility in how they assemble chiplets, prioritizing cost and yield for specific workloads.
According to a report first published by The Information, TSMC is pursuing this "EMIB-like" project, reportedly in collaboration with Kinsus. Unlike TSMC's flagship CoWoS (Chip-on-Wafer-on-Substrate) technology, which relies on large silicon interposers, Intel's EMIB approach uses small silicon bridges embedded directly into the package substrate. This method is generally more scalable and cost-effective, reducing the waste and expense associated with larger interposers.
The Shift to Panel-Level Packaging
Beyond the silicon bridge project, TSMC is accelerating its CoPoS (Chip-on-a-substrate) panel-level packaging platform. This initiative is designed to increase throughput and lower overall costs, addressing the growing bottleneck in the AI supply chain. While chip fabrication was once the primary hurdle, the AI boom has shifted the industry's focus toward advanced packaging—the complex process of integrating multiple chiplets and high-bandwidth memory into a single unit.
TSMC has already aggressively scaled its existing infrastructure to meet this demand. The company's CoWoS capacity has seen a compound annual growth rate (CAGR) of over 80% from 2022 to 2027, reflecting the massive volume of high-end GPUs and accelerators entering the market.
Industry Implications
This development validates Intel's packaging strategy, proving that the silicon bridge approach is a credible competitive force that the industry leader must now adopt. By diversifying its packaging options, TSMC can better serve a wider array of AI accelerators where peak bandwidth is less critical than manufacturing yield and price points.
For the broader market, the move suggests that the AI sector is large enough to support multiple packaging standards rather than a single monopoly. While Intel has secured a technological win in this specific niche, TSMC continues to maintain a dominant grip on the higher-value wafer manufacturing business that powers the majority of the world's AI hardware.
What to Watch
Industry observers will be monitoring the integration of the new silicon bridge technology into TSMC's production lines and the speed at which CoPoS reaches mass adoption. While the technical direction is clear, the exact timeline for when customers can migrate from CoWoS to these more cost-effective alternatives remains to be seen.